Investigation of dynamics in the comparator circuits of the subnanosecond analog-to-digital converter

Marcinkevičius, Albinas Jonas; Poviliauskas, Darius

Use this url to cite publication: https://hdl.handle.net/20.500.14911/132218

Investigation of dynamics in the comparator circuits of the subnanosecond analog-to-digital converter

Details

Publication Type (CRIS)

Straipsnis kitame recenzuojamame leidinyje / Article in other peer-reviewed edition (S5)

Publication Type (eLABa)

Straipsnis kitame recenzuotame leidinyje / Article in other peer-reviewed publication (S4)

Author(s)

Author	Affiliation
Marcinkevičius, Albinas Jonas	Elektroninių sistemų katedra / Department of Electronic Systems (0549)
Poviliauskas, Darius	Elektroninių sistemų katedra / Department of Electronic Systems (0549)

Title

Investigation of dynamics in the comparator circuits of the subnanosecond analog-to-digital converter

[en]

A. Marcinkevičius, D. Poviliauskas

Is part of

Электроника и связь : научно-технический журнал

Published In

Year	Issue	Start Page	End Page
2001	12	92	101

Publisher

Киев : КПI

Extent

p. 92-101

URI

URI
https://hdl.handle.net/20.500.14911/132218

Cited references

Science / Art Area

Technologijos mokslai / Technological sciences (T)

Field of Science / Art

Elektros ir elektronikos inžinerija / Electrical and electronic engineering (T001)

Keywords (en)

Abstract (en)

Theoretical substantiation of optimizing the microlayout of large-scale integration circuits of parallel subnanosecond analog-to-digital converters (ADC) is proposed. The mathematical model and methods of calculation of the layout structure of comparator signal circuits with distributed parameters are presented. The algorithm of computer formulation and solving of equations of transfer functions of comparator circuits and the investigation results of signal dynamic characteristics of the six-bit subnanosecond analog-to-digital converter developed according to the optimized layout of the chip are provided.