Acceleration of feature extraction for FPGA-based speech recognition

Arminas, Vytautas; Tamulevičius, Gintautas; Navakauskas, Dalius; Ivanovas, Edgaras

doi:10.1117/12.872081

Use this URL to cite this publication: https://hdl.handle.net/20.500.14911/127127

Acceleration of feature extraction for FPGA-based speech recognition

Details

Publication Type (CRIS)

Straipsnis konferencijos medžiagoje Web of Science duomenų bazėje / Article in conference proceedings in Web of Science database (P1a1)

Publication Type (eLABa)

Straipsnis konferencijos darbų leidinyje Web of Science DB / Article in conference proceedings Web of Science DB (P1a)

Author(s)

Author	Affiliation
Arminas, Vytautas	Elektroninių sistemų laboratorija / Laboratory of Electronic Systems (054902)
Tamulevičius, Gintautas	Elektroninių sistemų katedra / Department of Electronic Systems (0549)	Matematikos ir informatikos institutas
Navakauskas, Dalius	Elektroninių sistemų katedra / Department of Electronic Systems (0549)
Ivanovas, Edgaras	Elektroninių sistemų katedra / Department of Electronic Systems (0549)

Title

Acceleration of feature extraction for FPGA-based speech recognition

[en]

Vytautas Arminas, Gintautas Tamulevičius, Dalius Navakauskas, Edgaras Ivanovas

Is part of

Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments, Wilga, Poland, 24-29 June 2010 : proceedings

Published In

Year	Start Page	End Page
2010	1	6

Publisher

Bellingham : SPIE

Publisher (trusted)

The International Society for Optical Engineering

Referenced in Database(s)(DBs)

Conference Proceedings Citation Index - Science (Web of Science)

INSPEC

Extent

p. 1-6

URI

URI
https://hdl.handle.net/20.500.14911/127127

DOI

10.1117/12.872081

Cited references

Science / Art Area

Gamtos mokslai / Natural Sciences (N)

Field of Science / Art

Informatika / Informatics (N009)

Elektros ir elektronikos inžinerija / Electrical and electronic engineering (T001)

Keywords (en)

Abstract (en)

The paper describes a field programmable gate array implementation of the main part of speech recognition system - feature extraction. In order to accelerate recognition the whole cepstral analysis scheme is implemented in hardware by the use of intellectual property cores. Two field programmable gate array devices are used for evaluation. Comparative experimental results of four different implementations are presented. They grounds achieved 29 times faster speech analysis in comparison with software based analysis subsystem.